veriloghdl循环语法

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1、WhileLoop//Illustration1:Incrementcountfrom0to127.Exitatcount128.//Displaythecountvariable.integercount;initialbegincount=0;while(count<128)//Executelooptillcountis127.//exitatcount128begin$display("Count=%d",count);count=count+1;endend//Illustration2:Findthefirs

2、tbitwithavalue1inflag(vectorvariable)'defineTRUE1'b1';'defineFALSE1'b0;reg[15:0]flag;integeri;//integertokeepcountregcontinue;initialbeginflag=16'b0010_0000_0000_0000;i=0;continue='TRUE;while((i<16)&&continue)//Multipleconditionsusingoperators.beginif(flag[i])beg

3、in$display("EncounteredaTRUEbitatelementnumber%d",i);continue='FALSE;endi=i+1;endendForLoopintegercount;initialfor(count=0;count<128;count=count+1)$display("Count=%d",count);forloopscanalsobeusedtoinitializeanarrayormemory,asshownbelow.//Initializearrayelements'd

4、efineMAX_STATES32integerstate[0:'MAX_STATES-1];//Integerarraystatewithelements0:31integeri;initialbeginfor(i=0;i<32;i=i+2)//initializeallevenlocationswith0state[i]=0;for(i=1;i<32;i=i+2)//initializealloddlocationswith1state[i]=1;endRepeatLoop//Illustration1:increm

5、entanddisplaycountfrom0to127integercount;initialbegincount=0;repeat(128)begin$display("Count=%d",count);count=count+1;endend//Illustration2:Databuffermoduleexample//Afteritreceivesadata_startsignal.//Readsdatafornext8cycles.moduledata_buffer(data_start,data,clock

6、);parametercycles=8;inputdata_start;input[15:0]data;inputclock;reg[15:0]buffer[0:7];integeri;always@(posedgeclock)beginif(data_start)//datastartsignalistruebegini=0;repeat(cycles)//Storedataattheposedgeofnext8clock//cyclesbegin@(posedgeclock)buffer[i]=data;//wait

7、stillnext//posedgetolatchdatai=i+1;endendendendmoduleForeverloop//Example1:Clockgeneration//Useforeverloopinsteadofalwaysblockregclock;initialbeginclock=1'b0;forever#10clock=~clock;//Clockwithperiodof20unitsend//Example2:Synchronizetworegistervaluesateverypositiv

8、eedgeof//clockregclock;regx,y;initialforever@(posedgeclock)x=y;