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1、数字电路EDA技术复习资料1.用VHDL语言设计一个4输入同或门。libraryieee;useieee.std_logic_1164.all;entityyhm4isport(x1,x2,x3,x4:instd_logic;y:outstd_logic);end;architecturexofyhm4isbeginy<=x1xnorx2xnorx3xnorx4;end;2.在同一个VHDL文本中同时实现一个二输入的与门、或门、与非门、或非门、异或门及反相器的逻辑功能。libraryieee;u
2、seieee.std_logic_1164.all;entityljmisport(a,b:instd_logic;yand,yor,ynot,ynor,ynand,yxor:outstd_logic);end;architecturexofljmisbeginyand<=aandb;yor<=aorb;ynot<=nota;ynor<=anorb;ynand<=anandb;yxor<=axorb;end;3.用VHDL设计一个实现三输入端的多数表决器。libraryieee;useieee.
3、std_logic_1164.all;entitybjq3isport(a,b,c:instd_logic;y:outstd_logic);end;architecturexofbjq3issignalty:std_logic_vector(2downto0);第10页共10页beginty<=a&b&c;withtyselecty<='0'when"000",'0'when"001",'0'when"010",'1'when"011",'0'when"100",'1'when"101",'1'
4、when"110",'1'when"111",'X'whenothers;end;1.用并行信号赋值语句设计8选1数据选择器。libraryieee;useieee.std_logic_1164.all;entityxzq8isport(x:instd_logic_vector(7downto0);sel:instd_logic_vector(2downto0);f:outstd_logic);end;architectureaofxzq8isbeginf<=x(0)whensel="000"e
5、lsex(1)whensel="001"elsex(2)whensel="010"elsex(3)whensel="011"elsex(4)whensel="100"elsex(5)whensel="101"elsex(6)whensel="110"elsex(7)whensel="111"else'X';end;2.分别用IF语句和CASE语句设计3-8译码器。1）IF语句2）CASE语句libraryieee;useieee.std_logic_1164.all;entityde38ispo
6、rt(x:instd_logic_vector(2downto0);y:outstd_logic_vector(7downto0));end;libraryieee;useieee.std_logic_1164.all;entityde38_2isport(x:instd_logic_vector(2downto0);y:outstd_logic_vector(7downto0));end;第10页共10页architectureaofde38isbeginprocess(x)beginifx=
7、"000"theny<="00000001";elsifx="001"theny<="00000010";elsifx="010"theny<="00000100";elsifx="011"theny<="00001000";elsifx="100"theny<="00010000";elsifx="101"theny<="00100000";elsifx="110"theny<="01000000";elsifx="111"theny<="10000000";elsey<="XXXXXXXX"
8、;endif;endprocess;end;architectureaofde38_2isbeginprocess(x)begincasexiswhen"000"=>y<="00000001";when"001"=>y<="00000010";when"010"=>y<="00000100";when"011"=>y<="00001000";when"100"=>y<="00010000";when"101"=>y<="00100000";when"110"=>y<="01000000";whe
