数字系统设计mealy和moore型状态机编程

《数字系统设计mealy和moore型状态机编程》由会员上传分享，免费在线阅读，更多相关内容在行业资料-天天文库。

1、Mealy型modulemealy(clock,l,p,state);inputclock,l;outputp,state;regp;regstate;parameterhigh=1'b1,low=1'b0;initialbeginstate=low;p=0;endalways@(posedgeclock)case(state)low:if(!l)beginstate<=low;p<=0;endelsebeginstate<=high;p<=1;endhigh:if(!l)beginstate<=low;p<=0;endelsebeginstate<=high;p<=0;en

2、ddefault:beginstate<=low;p<=0;endendcaseendmoduleMealy型测试模块：`include"F:/verilog_homework/exercise_2/mealy/mealy.v"modulemealy_test;regclk,l;wireq;wirestate;initialclk=0;always#10clk=~clk;initialbeginl=1'b0;#20l=1'b1;#15l=1'b0;#40l=1'b1;endinitial#120$finish;mealym(.l(l),.clock(clk),.p(q),.s

3、tate(state));endmodule测试波形：Moore型：Verilog编程modulemoore(clock,state,in,p);inputin,clock;output[1:0]state;outputp;reg[1:0]state;assignp=state[0]&state[1];parameterll=2'b00,lh=2'b01,hh=2'b11;always@(posedgeclock)case(state)ll:if(!in)state<=ll;elsestate<=lh;lh:if(!in)state<=ll;elsestate<=hh;hh:

4、if(!in)state<=ll;elsestate<=hh;default:state<=ll;endcaseendmodule电路图Moore测试模块：`include"F:/verilog_homework/exercise_2/moore/moore.v"moduletest_moore;regclk,in;wire[1:0]state;wirep;initialclk=1'b0;always#10clk=~clk;initialbeginin=0;#10in=1'b0;#13in=1'b1;#18in=1'b1;#18in=1'b1;#25in=1'b0;#13in

5、=1'b1;endinitial#100$finish;moorem(.in(in),.p(p),.state(state),.clock(clk));endmodule测试波形：