Verilog 电子钟程序

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1、电子钟二、电子钟moduleclock(work_state,clock_on,clk_6MHz,clk_4Hz,in_set,display_set,clk_1024Hz,up,down,out1,out2,out3,out4,out5,out6,out7,out8,speaker);inputwork_state,clk_1024Hz,up,down,display_set,clk_6MHz,in_set,clock_on,clk_4Hz;outputout1,out2,out3,out4,out5,out6,out7,out8,speake

2、r;wire[2:0]in_set;reg[3:0]out1,out2,out3,out4,out5,out6,out7,out8;reg[2:0]display_state;reg[7:0]hour,minute,second,year,month,day,day_max;reg[7:0]hour_set,minute_set,second_set,day_set,month_set,year_set,day_set_max;integercentury=20;integeri=0;regspeaker;reg[7:0]clock_hour,c

3、lock_minute,clock_second;reg[3:0]high,med,low;reg[13:0]divider,origin;reg[7:0]counter;regout;wirecarry;//*****各初始值设置时对应的状态********//parameterstate_yorh=3'b100,//设置年或小时对应的按键状态state_morm=3'b010,//设置月或分对应的按键状态state_dors=3'b001;//设置日或秒对应的按键状态//***初始化时钟:08年08月08日00:00:00*****//ini

4、tialbeginyear<=8;year_set<=8;month<=8;month_set<=8;day<=8;day_set<=8;hour<=0;minute<=0;second<=0;clock_hour<=0;clock_minute<=0;clock_second<=0;display_state<=0;end//******电子钟正常工作状态下/work_state等于0时,时钟处于工作状态*******//always@(posedgeclk_1024Hz)//频率选择1024HZbeginif(i>=1023)begini<=

5、0;if(work_state)beginsecond<=second_set;minute<=minute_set;hour<=hour_set;day<=day_set;month<=month_set;year<=year_set;endelsebeginif(second>=59)beginsecond<=0;if(minute>=59)beginminute<=0;if(hour>=23)beginhour<=0;if(day>=day_max)beginday<=1;if(month>=12)beginmonth<=1;if(year

6、>=99)year<=0;elseyear<=year+1;endelsemonth<=month+1;endelseday<=day+1;endelsehour<=hour+1;endelseminute<=minute+1;endelsesecond<=second+1;endendelsei<=i+1;end//******数码管显示状态设置*******//always@(posedgedisplay_set)beginif(display_state>=2)display_state<=0;elsedisplay_state<=disp

7、lay_state+1;end//*闹钟模块设置，用clock_on控制闹钟，闹钟铃声播放时间为一分钟，可手动关闭闹钟**//always@(posedgeclk_6MHz)beginif(clock_on)beginif(clock_hour==hour&&clock_minute==minute)speaker<=out;elsespeaker<=0;endelsespeaker<=0;end//*************设置时钟的初值*************************///*用up来触发,当down=0时,一个上升沿触发来时

8、加1,否则减1.***/always@(posedgeup)beginif(!work_state)//时间处于正常工作状态时,使要设置